Device Family: Intel® Arria® 10 GT, Intel® Arria® 10 GX, Intel® Arria® 10 SX, Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: Intellectual Property


IP Product: PCI Express 1/2/4/8 Lanes (x8)

Why is the PCI Express MSI-X table missing and not enabled in my Configuration via Protocol (CvP) Init design?

Description

MSI-X capabilities will be disabled in Configuration via Protocol (CvP) initialization mode designs if the PCI Express® driver attempts to enumerate the device registers before the core is loaded. The MSI-X table requires the core to be loaded, since the memory for the table is found in the core image. The table is not available in the periphery CvP image.

Workaround/Fix

1)  Set up the MSI-X in the PCI Express variant being used and ensure MSI-X is enabled
2)  Load the periphery image via flash
3)  When in the OS, load the core image via software driver (i.e. quartus_cvp)
4) If a prior driver was setup,

4a) Uninstall and reinstall the driver for PCI Express
OR
4b) Disable and re-enable the driver

Observe that the MSI-X table is set up and interrupts can be observed on the link.