Device Family: Arria® V GT, Arria® V GX, Arria® V ST, Arria® V SX, Cyclone® V E, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller Supporting UniPHY

Are there any issues with the UniPHY LPDDR2 IP address and command pinout ?

Description

In the 12.0 version of the External Memory Interface Handbook : Volume 2 Chapter 3 "Planning Pin and FPGA Resources" Table 3-14 has incorrect information for the Address and Command Pinout.

Workaround/Fix

It states the address and command pins can be placed on "Any user I/O pin".

The correct placement details are "Place all the address and command pins in a single x8/9 DQ/DQS group".

12 pins are required : mem_ca[9:0], mem_cke[0] and mem_cs_n[0]

This will be corrected in a future version of the EMI Handbook.