Device Family: Intel® Arria® 10 GT, Intel® Arria® 10 GX, Intel® Arria® 10 SX, Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Cyclone® V GT, Cyclone® V GX, Cyclone® V ST, Cyclone® V SX, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: Intellectual Property


IP Product: PCI Express 1/2/4/8 Lanes (x8)

How do I generate a downstream hot reset from the Altera Hard IP for PCI Express Avalon-ST Root Port?

Description

The PCI Express® Specification Revision 3.0 describes a Hot Reset and how it is signaled on the link.

In the Altera® Root Port, setting bit[6] Secondary Bus Reset of the Bridge Control Register (0x03E), causes a Hot Reset. Refer to Section 7.5.3.6 of the PCIe Spec Revision 3.0.

This is a Type 1 Configuration Space register, which is accessed by issuing a Type 0 Configuration TLP.

Workaround/Fix