You may see a warning message of this type in Qsys when using External Memory Interface (EMIF) IP with the Memory Parameters > Enable DM pins checkbox deselected.
This is due to a mismatch between the data bus widths of the Avalon® MM master and the Avalon MM slave EMIF IP. When the DM pins are not used, the byteenable ports are not available on the EMIF IP Avalon slave interface.
Each write from the Avalon-MM master data bus width is narrower than the EMIF IP Avalon-MM data bus width and when the Avalon-MM master performs a write, it will be to the entire data width of the EMIF IP.
For example if the Avalon-MM master data width is 32 bits and the EMIF IP Avalon-MM slave data width is 256 bits, data in the other 224 bits will also be written to the external memory which may not be what the user intended.