Device Family: Intel® Arria® 10 GT, Intel® Arria® 10 GX, Intel® Arria® 10 SX, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

<slave_name>.ctrl_amm_avalon_slave_0 does not have byteenables. Writes from narrow master <master_name>.master may result in data corruption

Description

You may see a warning message of this type in Qsys when using External Memory Interface (EMIF) IP with the Memory Parameters > Enable DM pins checkbox deselected.

This is due to a mismatch between the data bus widths of the Avalon® MM master and the Avalon MM slave EMIF IP. When the DM pins are not used, the byteenable ports are not available on the EMIF IP Avalon slave interface.

Each write from the Avalon-MM master data bus width is narrower than the EMIF IP Avalon-MM data bus width and when the Avalon-MM master performs a write, it will be to the entire data width of the EMIF IP.

For example if the Avalon-MM master data width is 32 bits and the EMIF IP Avalon-MM slave data width is 256 bits, data in the other 224 bits will also be written to the external memory which may not be what the user intended.

Workaround/Fix

To avoid data corruption on writes, match the Avalon data bus widths of the Avalon master and the Avalon slave EMIF IP or use the EMIF IP byte enable option.

The warning message is planned to be enhanced in a future version of the Quartus® II software.