Device Family: Cyclone® V E

Type: Answers

Area: Component, EMIF


IP Product: DDR3 SDRAM Controller Supporting UniPHY

Why do I see the drv_status_fail bit assert when I simulate the LPDDR2 example design in Skip Calibration mode?

Description

You may see the drv_status_fail signal assert high when you simulate the LPDDR2 example design in Skip Calibration mode. The LPDDR2 controller requires an adjustment to the DQS window, which is only provided in Quick Calibration and Full Calibration modes.

Workaround/Fix

The workaround is to enable either Quick Calibration or Full Calibration mode when you generate the IP.