Device Family: Intel® Arria® 10 GT, Intel® Arria® 10 GX, Intel® Arria® 10 SX, Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Cyclone® V E, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: Intellectual Property


IP Product: PCI Express 1/2/4/8 Lanes (x8)

Why do I see this message when simulating the Altera Hard IP for PCI Express: # FATAL: Current Link Speed is Unsupported?

Description

You will see this message if you create your own Qsys project using an Avalon®-ST variant of the PCI® Express Hard IP core and do not include the Altera® example application (Titled "APPS" in the Altera created example designs), and do not drive the pld_core_ready signal on the Hard IP instantiation.

The full set of messages look like this:
# FATAL:          <sim time>   Current Link Speed is Unsupported                                                           
#                                  FAILURE: Simulation stopped due to Fatal error!

Workaround/Fix

Drive the pld_core_ready signal on the Hard IP core instantiation to 1\'b1.