Article ID: 000076226 Content Type: Troubleshooting Last Reviewed: 08/15/2023

Why can't some DDR3 HMC control registers be read or written by the CSR interface?

Environment

  • Quartus® II Software
  • DDR3 SDRAM Controller with UniPHY Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    There is an issue while using the CSR interface to read and write DDR3 hard memory controller (HMC) control registers in both simulation and lab for the Cyclone® V and Arria® V devices. Some DDR3 HMC control registers can't be read back or written in.

    The Controller Register map in Table 5-18 in the external memory interface handbook is for the DDR3 soft memory controller, and not for the DDR3 HMC.

    Resolution

    This issue has been fixed in the current release of the external memory interface handbook.

    Related Products

    This article applies to 2 products

    Arria® V FPGAs and SoC FPGAs
    Cyclone® V FPGAs and SoC FPGAs