Device Family: Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property

IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Why is a global signal assignment to <instance_name>|s0|rst_controller|alt_rst_sync_uq1|reset_out being ignored by my UniPHY-based DDR3 controller IP?


After the UniPHY-based DDR3 IP pin_assignments.tcl script is run and the project compiled, the Quartus® II software Ignored Assignments Fitter report incorrectly shows a global signal assignment to the reset signal <instance_name>|s0|rst_controller|alt_rst_sync_uq1|reset_out.


This ignored global assignment is due to a legacy code assignment and can be ignored. It is planned to be fixed in a future version of the Quartus II software.