Device Family: Intel® Arria® 10 GT, Intel® Arria® 10 GX, Intel® Arria® 10 SX, Intel® Cyclone® 10 GX

Intel Software: Quartus II, Quartus Prime Standard

Type: Answers

Area: Intellectual Property


Last Modified: August 06, 2018
Version Found: v15.0
Version Fixed: v16.1
IP Product: PCI Express 1/2/4/8 Lanes (x8)
Bug ID: FB: 309656;

Warning (10240): Verilog HDL Always Construct warning at altpciexpav_stif_txresp_cntrl.v

Description

Due to a problem in the Intel® Arria® 10 Hard IP for PCI Express*, you will see the following warnings during analysis and elaboration when using the Intel® Quartus® II or Intel® Quartus® Prime Standard software.

Warning (10240): Verilog HDL Always Construct warning at altpciexpav128_txresp_cntrl.v(344): inferring latch(es) for variable "payload_limit_cntr", which holds its previous value in one or more paths through the always construct
Info (10041): Inferred latch for "payload_limit_cntr[0]" at altpciexpav128_txresp_cntrl.v(344)
Info (10041): Inferred latch for "payload_limit_cntr[1]" at altpciexpav128_txresp_cntrl.v(344)
Info (10041): Inferred latch for "payload_limit_cntr[2]" at altpciexpav128_txresp_cntrl.v(344)
Info (10041): Inferred latch for "payload_limit_cntr[3]" at altpciexpav128_txresp_cntrl.v(344)

Workaround/Fix

These warning can be safely ignored, and have been fixed in Intel® Quartus® Prime Pro software starting in version 16.1.