Nios® II Classic and Nios II Gen2 processors are binary compatible, but there have been some minor changes to the HAL and cache functionality so it is recommended that BSPs and software be re-built with tools/libraries from the latest release (v14.0+), and if the processor configuration contains a data cache, that the use of uncached memory transactions in all user software be reviewed.
Uncached Memory Regions
When a processor with a data cache issues a read and the data is not in the cache, the cache will usually load a small block or ‘line’ of data from memory into the cache. When the processor issues a write, the new value is usually stored in the data cache; with a write back data cache (e.g. as in the Nios II processor) new data values are only written back to the real physical location when the cache is flushed or data is evicted from the cache. This kind of operation is not acceptable for regions of memory where the data must be written immediately to the hardware to effect the function/operation desired (e.g. shared memory or writes to peripheral/hardware control registers). This means that developers are required to either flush the cache immediately, or use a memory operation that bypasses the cache and goes directly/immediately to the hardware (preferred). Sometimes there are may be other reasons why the developer does not want the data to be cached (e.g. if the data is never to be read back and/or it is not desirable to evict other data from the cache for performance or other reasons).
With the Nios II Classic processor cache bypass can be achieved by using special I/O read/write instructions (e.g. ldwio/stwio), by setting bit-31 in the memory address of the read/write address, or by implementing an MMU/MPU and setting it up appropriately. (Note: MMU and bit-31 options are mutually exclusive)
Nios II Gen2 cores offer the same mechanisms for cache bypass but the implementation is slightly different and could be a potential issue with Nios II Classic to Nios II Gen2 software migration.
If the Nios II Classic processor performs an uncached write and the memory location (and hence associated cache line) is present in the data cache, the new data value is also written to the cache (despite this being an uncached write). This means that the data in the cache is always up to date, and if the software design causes regions of uncached memory to be loaded into the cache there is no loss of data coherency. Hence the Nios II Classic processor can also support uncached memory regions of any size and any address alignment (as it allows mixing of cached and uncached regions of memory on the same cache line). This is not true for Nios II Gen2 cores.
In the Nios II Gen2 processor core, uncached transactions truly bypass the data cache and cache contents are not updated (standard practice for most processors). If an uncached memory region shares a cache line with a cached region, the uncached region will be mapped into the cache and may be updated with old/garbage data when the cache is flushed. Developers have to ensure that uncached and cached memory regions are clearly separated and do not share the same cache line when mapped into the in the cache. This is achieved by ensuring that uncached memory regions are aligned to the size of the data cache line (32 bytes) and are the size of one or more data cache lines (multiples of 32 bytes). This prevents mixing of cacheable and non-cacheable data on the same cache line and hence write back of stale/invalid data. Good design practice recommends that base addresses of peripheral register sets are aligned with the data cache line boundaries and that drivers use the cache bypass I/O read write instructions - so it is unlikely that modifications to drivers will be required. Other software that uses cache bypass/uncached memory regions should be checked carefully to ensure that cache lines do not map to regions containing both cached and uncached data.
Note: Software that uses the bit-31 cache bypass feature will no longer work if the Nios II Gen2 32-bit address range option is selected, the cache bypass I/O instructions or the peripheral memory region should be used instead.
Developers should consider the potential effects of use of the new 32-bit address range and peripheral memory region options in case the hardware configuration is changed to use them. The software should be modified to support these features or detect them and issue error messages.
Software that uses the bit-31 cache bypass feature will no longer work if the Gen2 32-bit address range option is selected, the cache bypass I/O instructions or the peripheral memory region should be used instead.
If the Nios II Classic ECC option was supported in the original software it will need to be extended to include the additional memories supported by the Nios II Gen2 processor.