Device Family: Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

How do I access the UniPHY CSR registers?

Description

In Quartus® II software and IP version 11.0, there is an issue accessing the Control and Status registers in the UniPHY based memory controller.

The latest External Memory Interface (EMIF) handbook shows the UniPHY register map and Controller register map as 9-bit addresses (UniPHY at 0x000 and Controller at 0x100). In the actual implementation, the controller CSR address width is 19-bits and the addresses for the register maps specified in the EMIF handbook are incorrect. The following table outlines the correct register maps for 11.0:

UniPHY Register Map

EMIF Handbook Incorrect Address

Correct Address

Description

0x001

0x0_0004

Reserved

0x004

0x0_0010

UniPHY Status Register 0

0x005

0x0_0014

UniPHY Status Register 1

0x006

0x0_0018

UniPHY Status Register 2

0x007

0x0_001C

UniPHY Memory Init Param Reg 0

Controller Register Map

EMIF Handbook Incorrect Address

Correct Address

Description

0x100

0x4_0000

ALTMEMPHY status/control register

0x110

0x4_0040

Controller status/config register

0x120

0x4_0080

Memory address size register 0

0x121

0x4_0084

Memory address size register 1

0x122

0x4_0088

Memory address size register 2

0x123

0x4_008C

Memory timing parameter register 0

0x124

0x4_0090

Memory timing parameter register 1

0x125

0x4_0094

Memory timing parameter register 2

0x126

0x4_0098

Memory timing parameter register 3

0x130

0x4_00C0

ECC control register

0x131

0x4_00C4

ECC status register

0x132

0x4_00C8

ECC error address register

This issue is fixed in the Quartus II software version 11.1.