This error message occurs when using :
- The Altera QDRII and QDRII+ SRAM Controller with UniPHY IP
- Interfacing to a QDRII+ component with a read latency of 2
Due to the internal structure of the IO elements of Arria® II GX, Stratix® III and Stratix IV devices, the CQ and CQn signal connections have to be swapped over when interfacing to a QDRII+ SRAM component with a read latency of 2.
Connect the read clocks :
- QDRII+ SRAM component CQ pin -> FPGA CQn pin (marked Qbar in pin planner)
- QDRII+ SRAM component CQn pin -> FPGA DQS pin (marked S in pin planner)
For QDR II or QDR II+ SRAM devices with 1.5 or 2.5 cycles of read latency, connect CQ to DQS pin (S in the Quartus II Pin Planner), and CQn to CQn pin (Qbar in the Quartus II Pin Planner).