The low read efficiency is caused by one of the settings in Altera® DDR3 controller for quarter rate design. When the read latency is longer (e.g: larger CAS latency number), the controller will stall internal read commands from executing because the maximum number of pending read commands is reached.
Device Family: Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX
Area: EMIF, Intellectual Property
The current workaround for this issue is to change the parameter MAX_PENDING_RD_CMD from 16 to 32 in <instance_name>_c0.v file as shown below:
MAX_PENDING_RD_CMD = 16
MAX_PENDING_RD_CMD = 32
This issue will be fixed in a future release of the Quartus® II software.