Device Family: Arria® V GT

Device Family: Arria® V GX

Device Family: Arria® V GZ

Device Family: Arria® V ST

Device Family: Arria® V SX

Device Family: Cyclone® V E

Device Family: Cyclone® V GT

Device Family: Cyclone® V GX

Device Family: Cyclone® V SE

Device Family: Cyclone® V ST

Device Family: Cyclone® V SX

Device Family: Stratix® III

Device Family: Stratix® IV E

Device Family: Stratix® IV GT

Device Family: Stratix® IV GX

Device Family: Stratix® V E

Device Family: Stratix® V GS

Device Family: Stratix® V GT

Device Family: Stratix® V GX

Type: Answers

Area: EMIF

Area: Intellectual Property


IP Product: RLDRAM II Controller with UniPHY

Why do I get a no-fit when using the Altera External Memory Interface IP in an FPGA device that has a relatively low number of IO banks?

Description

When compiling the DDR3, DDR2, LPDDR2, QDRII or RLDRAM II Controller with UniPHY IP using an FPGA device that has relatively low number of IO banks, you may experience a no-fit and possibly the following Quartus® II error. 

Error (175020): Illegal constraint of fractional PLL to the region

The problem occurs if all the IO banks on a certain side of the FPGA have been fully used by the memory interface and the PLL input reference clock and other miscellaneous memory interface pins do not have the same IO standard as the memory interface IO.

Workaround/Fix

Set the PLL input reference clock and other miscellaneous memory interface pins to have same IO standard as the memory interface IO.