Article ID: 000079291 Content Type: Troubleshooting Last Reviewed: 08/15/2023

Is there a way to choose which rank to be calibrated first in the multiple-rank DDR3 SODIMM design?

Environment

  • Intel® Quartus® Prime Design Software
  • DDR3 SDRAM Controller with UniPHY Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Is there a way to choose which rank to be calibrated first in the multiple-rank DDR3 SODIMM design?

     

     

    Resolution

    No, there is no way to control which rank is to be calibrated first. For multiple ranks design, multiple ranks are calibrated at the same time in some of the calibration stages.

    Related Products

    This article applies to 11 products

    Cyclone® V GX FPGA
    Cyclone® V SE SoC FPGA
    Arria® V SX SoC FPGA
    Arria® V GZ FPGA
    Arria® V GT FPGA
    Stratix® V GX FPGA
    Stratix® V E FPGA
    Cyclone® V ST SoC FPGA
    Stratix® IV E FPGA
    Stratix® V GS FPGA
    Stratix® V GT FPGA