Device Family: Intel® Arria® 10 GT, Intel® Arria® 10 GX, Intel® Arria® 10 SX, Arria® II GX, Arria® II GZ, Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Arria® GX, Cyclone® III, Cyclone® III LS, Cyclone® IV E, Cyclone® IV GX, Cyclone® V E, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX, Intel® Stratix®, Stratix® II, Stratix® II GX, Stratix® III, Stratix® IV E, Stratix® IV GT, Stratix® IV GX, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: Component



Why does the PFL fail to configure the FPGA when the flash is programmed with a .map.flash file?

Description

The Parallel Flash Loader (PFL) IP may fail to configure the FPGA when the flash is programmed with a .map.flash file, due to the lack of the .pof version byte in this file.

You can generate the .flash file and the .map.flash file for PFL using the sof2flash command.  Whilst the .map.flash file contains option bits for the PFL, it lacks the .pof version byte which is necessary for the PFL.

For detail about option bits format, see Parallel Flash Loader IP Core User Guide (PDF)

Workaround/Fix

To work around this, program the .pof version manually at the offset address of 0x80 from the start address of the option bits.  When the enhanced bitstream-compression feature isn\'t enabled, the value for the .pof version is 0x03.  When the enhanced bitstream-compression feature is enabled, the value for the .pof version is 0x04.