Type: Answers


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Why do I get the following error during the Fitter stage: Termination logic option is set to Differential for input <name of PLL reference clock pin>, but setting is not supported by I/O standard <single-ended I/O standard>?

Description

Starting in the Quartus Prime software version 16.0, you may see this error message during the Fitter stage when the design instantiates an External Memory Interface IP generated in 16.0 and later:

Termination logic option is set to Differential for input <name of PLL reference clock pin>, but setting is not supported by I/O standard <single-ended I/O standard>

The error occurs if you configure the External Memory Interface IP such that the "PLL reference clock I/O standard" setting uses the "LVDS with On-Chip Termination" value, and the .QSF file explicitly overrides the PLL reference clock pin to use a non-LVDS I/O standard (e.g. 1.2-V). 

The error occurs because starting in 16.0, the External Memory Interface IP explicitly enables "Differential" input termination for the PLL reference clock in the IP's .QIP file if the "LVDS with On-Chip Termination" is used. Differential input termination is not supported by non-LVDS I/O standard.

Workaround/Fix

To resolve this error, you can do one of the following:

1) Add a new assignment in the .QSF file to explicitly disable the input termination for the PLL reference clock. For example:

set_instance_assignment -name INPUT_TERMINATION OFF -to <name of PLL reference clock pin>

2) Re-configure and re-generate the IP such that you specify the desired single-ended I/O standard (e.g. 1.2-V) for the PLL reference clock I/O standard.

3) If you actually intend to use the LVDS I/O standard for the PLL reference clock (which is recommended due to better noise rejection compared to single-ended I/O standard), simply remove the assignment in the .QSF file that sets the PLL reference clock I/O standard.