You may see a simulation failure when you parameterize UniPHY based DDR3 IP and simulate its auto-generated example design if you have followed the steps below:
1) Enable 'Advanced clock phase control' in a MegaWizard PHY setting
2) Set a value other than zero in 'Additional CK/CK# phase'
3) Disable 'Advanced clock phase control'
4) Generate the IP and example design