Device Family: Arria® V GT

Device Family: Arria® V GX

Device Family: Arria® V ST

Device Family: Arria® V SX

Device Family: Cyclone® V E

Device Family: Cyclone® V GT

Device Family: Cyclone® V GX

Device Family: Stratix® III

Device Family: Stratix® IV E

Device Family: Stratix® IV GT

Device Family: Stratix® IV GX

Device Family: Stratix® V E

Device Family: Stratix® V GS

Device Family: Stratix® V GT

Device Family: Stratix® V GX

Type: Answers

Area: EMIF

Area: Intellectual Property

IP Product: RLDRAM II Memory Controller

Why is my Qsys UniPHY based memory controller missing the pin_assignments.tcl file and other support files?


There is a known issue with multiple instantions of the same UniPHY based memory controller in a Qsys system. The Qsys optimization step only creates the pin_assignments.tcl file and other support files for the original controller and reuses these files for all other instances of the same controller.


The workaround is to make a trivial change to a non-critical parameter in the UniPHY core so that Qsys will recognize the core as unique and will generate all the appropriate files. The simplest change is to modify one of the board skew parameters in the Board Settings tab by 0.001ps. For example, change the "Maximum CK delay to DIMM/device" from 0.6ns to 0.599ns.

Once you make all instances of the UniPHY controller unique, regenerate the Qsys system and each instance should have its own set of files.

This issue will be fixed in a future version of the Quartus®  II software.