Device Family: Stratix® V GT

Type: Answers

Area: Intellectual Property


IP Product: 10Gb Ethernet MAC Megacore

What is the definition of the avalon_st_txstatus_error signals from the 10-Gbps Ethernet MAC MegaCore function?

Description

The description of the avalon_st_txstatus_error signals is missing from the 10-Gbps Ethernet MAC MegaCore® Function User Guide.

The definition for the avalon_st_txstatus_error signals is not the same as for the avalon_st_rxstatus_error signals.

Please refer to the two sets of error descriptions given below, for full details:

When set to 1, each bit of this bus indicates an error type in the respective Transmit/Receive frame.

TX Status Error

. Bit 0: Undersized frame.
. Bit 1: Oversized frame.
. Bit 2: Payload length error.
. Bit 3: Not Used.
. Bit 4: Underflow.
. Bit 5: Avalon-ST TX Error.
. Bit 6: Not Used.
 

RX Status Error

. Bit 0: Undersized frame.
. Bit 1: Oversized frame.
. Bit 2: Payload length error.
. Bit 3: CRC Error.
. Bit 4: Not Used.
. Bit 5: Not Used.
. Bit 6: PHY Error.

The IP core presents the error status on the bus in the same clock cycle it asserts the valid signal. The error status is invalid when an overflow occurs or when CRC and/or padding removal is enabled.

Another error in the user guide is the definition for avalon_st_txstatus_valid. This signal definition should be: "When asserted, this signal indicates that avalon_st_txstatus_data[] contains valid information about the Transmit frame."

This information will be included in a future release of the 10-Gbps Ethernet MAC MegaCore Function User Guide.