Device Family: Stratix® IV

Device Family: Stratix® IV GX

Type: Answers

Area: Development Kits



Are there any known issues with the Stratix IV GX Development Kit?

Description

Programming with EthernetBlaster

This problem affects Rev A and Rev B production boards of the Stratix® IV GX Development Kit which contain a p/n sticker that end in -EN130A, -EN140A, or -0A (e.g. 6XX-41284R-0A). The p/n sticker is located on the metal PCI Express bracket. Newer boards use an ON Semiconductor (NLAS4717EPMTR2G) which does not exhibit this problem.

The EthernetBlaster uses a higher clock rate than the embedded USB-Blaster™ download cable. The development board has the MAX® II device in the JTAG chain and the TDO output cannot drive the capacitance of the switches hard enough for the JTAG chain to operate at the higher speed.

To enable programming of the FPGA through the use of the EthernetBlaster, switch the MAX II device out of the JTAG chain. This can be done by setting position 1 of the JTAG switch (Rev A - SW4 or Rev B - SW6) to the "ON" position.

Extra pin "fsm_d32"

The 32-bit FSM data bus is named fsm_d[31:0]. The extra pin fsm_d32 pin, which is found in the BUP design example, is not specified in Stratix IV GX development board reference manual or the board schematic.

The following critical warning will be reported during Quartus® II fitter run. Remove the redundant pin fsm_d32 from the design example to remove the critical warning.

Critical Warning reported by fitter run:

Critical Warning: No exact pin location assignment(s) for 1 pins of 111 total pins

Info: Pin fsm_d[32] not assigned to an exact location on the device

This problem will be fixed in a future development kit release.

BUP loading user software image

There is a bug in the Stratix IV GX Development Kit Board Update Portal (BUP) design which prevents user software from being loaded by your Nios® II processor. User hardware images are not affected, nor are the factory images. Affected versions include the development kit installer for Quartus II software versions 9.0, 9.0 SP1, and 9.1. This bug will be fixed in a future development kit release.

The problem is in reconfig_utils.h which is part of the BUP design web_server in the software_examples directory. Lines 51 and 52 incorrectly read:

//#define USER_SW_IMAGE_OFFSET         0x02820000
#define USER_SW_IMAGE_OFFSET         0x02800000

These lines should read:

#define USER_SW_IMAGE_OFFSET         0x02820000
//#define USER_SW_IMAGE_OFFSET         0x02800000

This causes the user created software flash file to be programmed to the wrong location in the CFI flash when using the BUP design to program the user images. To fix the problem, you can either recompile the factory software or download the corrected factory software image attached here, and reprogram the factory software image on your development kit.

To recompile the factory software, first run create-this-app from the web_server directory found in software_examples in the BUP source files. Next, create a .flash file from the .elf using the following command:

elf2flash --base=0x0a000000 --end=0x0bffffff --reset=0x02020000 --input=web_server.elf --output=web_server.flash --/components/altera_nios2/boot_loader_cfi.srec

To reprogram the factory software image to the CFI flash, use the following command in the same directory as web_server.flash:

nios2-flash-programmer -b 0x0a000000 web_server.flash

After programming the factory software image, power cycle the board and follow the instructions for loading a factory hardware and software image using the BUP web page. If the above process does not work, your CFI flash may not contain the factory images. Follow the development kit user guide on restoring the factory flash contents, and repeat the above process.