Device Family: Cyclone® II

Type: Answers

Area: Component, EMIF



Are there any issues with the DDR/DDR2 specification for Cyclone II C7 and C8 speed grades that were published in AN 361: Interfacing DDR & DDR2 SDRAM With Cyclone II Devices version 1.0?

Description

Yes.  In version 1.0 of AN 361: Interfacing DDR & DDR2 SDRAM With Cyclone II Devices, the DDR/DDR2 maximum frequency specifications for the Cyclone II C7 and C8 were incorrectly listed as follows
DDR2 Specifications Published in AN361v1.0
C6: 167MHz (correct at posted)
C7 : 167MHz (too aggressive)
C8 : 133MHz (too aggressive)

These initial specifications were based on simple read/write timing analysis and did not include I/O toggle limitations, noise sources and other factors.  As a result, the claim for DDR/DDR2 maximum frequency operation appeared more aggressive then is achievable in a system.

Altera has completed a more rigorous bottleneck analysis, and has updated the Cyclone II DDR/DDR2 speeds as follows:
Achievable Cyclone II DDR2 Speeds
C6 : 167MHz
C7 : 150MHz
C8 (VIO) : 125MHz 
C8 (HIO) : 100MHz 

Achievable Cyclone II DDR Speeds

C6 : 167MHz
C7 : 150MHz
C8 : 125MHz  

It should be noted that although the original maximum frequency claim on the web was more aggressive than achievable, any user attempting to achieve these speeds would be flagged by the Quartus II software with an indication that their requested frequency was too high.  e.g. if your Cyclone II C8 / DDR2 design was set for 125MHz, the following warning would be issued "Warning: DQS Frequency setting 125.0 MHz of DQS I/O pin ddr_dqs[0] should be less than 100.0 MHz"

See the solution titled "Why am I receiving a warning message when I compile for the advertised DDR/DDR2 speeds in the -7 and -8 speed grade Cyclone II FPGAs in Quartus II versions 5.0SP1 and lower?" for more details

Ensure your design targets are based on the updated system numbers listed in version 1.1 of AN361 and ensure you perform a timing analysis for your unique system to define your actual system speed.