Device Family: Cyclone® II

Type: Answers

Area: Component, EMIF

IP Product: DDR2 SDRAM Controller

Why am I receiving a warning message when I compile for the advertised DDR2 speeds in the -7 and -8 speed grade Cyclone II FPGAs in Quartus II versions 5.0SP1 and lower?


Quartus II versions 5.0SP1 and lower will display a warning if you exceed any of the following parameters when you compile your SSTL18-C1 DDR2 / Cyclone II design:

For example, if your Cyclone II C8 / DDR2 design is set for 125MHz, the following warning will be issued "Warning: DQS Frequency setting 125.0 MHz of DQS I/O pin ddr_dqs[0] should be less than 100.0 MHz".

The data used for the Quartus II limitations listed above were predicted values based on Cyclone II I/O simulations. However, recent Cyclone II I/O characterization has proven SSTL-18 (the I/O standard required for DDR2) to operate beyond the expectations previously defined and used in Quartus II. As a result of this characterization data and further detailed analysis, both the DQS Fmax limitation and the published DDR2 specifications will be updated as follows: Updated DDR2 Specification Updated DQS Fmax Limitations C6 : 167MHz C7 : 150MHz C8 : 125MHz Because the current version of Quartus II only lists this as a Warning and not an Error, there is no workaround required and you can target Altera's advertised speeds by simply ignoring this particular warning when you are targeting a valid system speed above.