Device Family: Arria® V ST

Device Family: Arria® V SX

Device Family: Cyclone® V SE

Device Family: Cyclone® V ST

Device Family: Cyclone® V SX

Type: Answers

Area: Embedded



Why does my Cyclone V SoC or Arria V SoC design hang on boot or fail SDRAM calibration?

Description

Due to a problem, Cyclone® V SoC and Arria® V SoC devices may encounter the following issues for configurations with clock select (CSEL) pins set to values of  01, 10 or 11:

  1. The HPS hangs during the BootROM stage and is unable to proceed to the Preloader stage.
  2. HPS SDRAM calibration fails during the Preloader process.

Workaround/Fix

A patch for the Quartus® II software / SoC EDS versions 13.1 and 14.0 is available to work around this problem,  follow the instructions below.

  1. Download and install the patch from the appropriate link below

  2. Connect the CSEL pins [1:0] to pull-down to ground resistors (4.7 kohm to 10 kohm) on the board, CSEL=00. In this CSEL mode the BootROM does not perform PLL configuration and the PLLs are in by-pass state upon power-up or cold reset.

  3.  

  4. Regenerate the Preloader image
    1. Launch embedded command shell
      • On Windows systems, run the batch file:  <SoCEDS installation Folder>\embedded\Embedded_Command_Shell.bat
      • On Linux systems, run the shell script:  <SoCEDS installation Folder>\embedded\embedded_command_shell.sh
    2. In the command shell, change directory to <your_design_path>/software/spl_bsp
    3. Type make clean-all
      • Note: This command removes the Preloader binary image and the uboot-socfpga folder which contains all Preloader source files. If you modified or added files into this folder previously,you should back-up those files and re-apply them after using this patch.
    4. Type make
      • Note: Re-making the Preloader invokes extracting the Preloader source files from SoC EDS installation directory which contains the fix to this issue.