For DDR3 UniPHY controllers, the width of the Avalon data bus depends on the Rate on Avalon-MM interface setting of the controller. The options are half-rate or quarter-rate. A half-rate controller has an Avalon data width 4 times as large as the external data bus width. A quarter-rate controller has an Avalon data width 8 times as large as the external data bus.
When ECC is enabled, the DDR3 UniPHY controller will add an additional 8-bits on the external data bus for the ECC code word. This ECC code word occupies the most significant 8-bits of the external data bus.
For example, if you generated a 64-bit DDR3 quarter-rate controller with ECC, then the Avalon data bus would be 512-bits wide and the external data bus would be 72-bits wide (64-bits data 8-bit ECC code word). Each Avalon write burst of 1 will result in a burst length 8 (BL8) transfer on the external data bus. The Avalon data bus is mapped to the external data bus as follows:
External data 0 [71:0] = {ECC code word 0[7:0], Avalon data[63:0]}
External data 1 [71:0] = {ECC code word 1[7:0], Avalon data[127:64]
External data 2 [71:0] = {ECC code word 2[7:0], Avalon data[191:128]
External data 3 [71:0] = {ECC code word 3[7:0], Avalon data[255:192]
External data 4 [71:0] = {ECC code word 4[7:0], Avalon data[319:256]
External data 5 [71:0] = {ECC code word 5[7:0], Avalon data[383:320]
External data 6 [71:0] = {ECC code word 6[7:0], Avalon data[447:384]
External data 7 [71:0] = {ECC code word 7[7:0], Avalon data[511:448]