No, the local-to-memory address mapping cannot be changed in the HPS DDR3 controller simulation fileset. The default local-to-memory address mapping for the HPS DDR3 controller is CHIP_ROW_BANK_COL in both the synthesis and simulation filesets.
Device Family: Arria® V ST, Arria® V SX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX
Area: EMIF, Intellectual Property
IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY