Device Family: Arria® V, Arria® V GX

Type: Answers

Area: Component, EMIF


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Error (175020): Illegal constraint of pin to the region : no valid locations in region

Description

In Arria® V devices, some differential pairs only have one of the signals in a DQ group.

When a differential pair of this type is used for the memory clock in UniPHY IP, in the Quartus® II software version 11.1 releases, the placement achieves a successful fit. However, in the Quartus II software version 12.0 release, the placement results in a fitter error message of the type shown above.  

Workaround/Fix

In the UniPHY IP file  xxx_addr_cmd_pads.v, find the localparam declaration of USE_ADDR_CMD_CPS_FOR_MEM_BK and change it from false to true.

Recompile the project.

The recommendation for optimum timing is to place both pins of the memory clock differential pair in a DQ group, but in future versions of Quartus II software, a successful fit should also be achieved when only one of the pins is in the DQ group.