Device Family: Stratix® III, Stratix® IV E, Stratix® IV GT, Stratix® IV GX, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Why does the Avalon bus lock up when simulating a DDR2 SDRAM and DDR3 SDRAM Controller with UniPHY generated in version 11.0?

Description

DDR2 SDRAM and DDR3 SDRAM UniPHY based Controller version 11.0 with the Control and Status Register (CSR) Interface enabled causes the Avalon bus to lock up in Modelsim simulations. After an Avalon read or write transaction, the WAITREQUEST signal asserts high and stays asserted indefinitely, not allowing other read or write transactions on the Avalon bus.

The problem is in the alt_mem_ddrx_csr.v file. There are bus width mismatches in the file that leads to unconnected bits to certain configuration ports.

The workaround is to download the attached version of the alt_mem_ddrx_csr.v file and overwrite the four instances in the following directories:

corename/

corename_sim/altera_mem_if_nextgen_ddr3_controller_core/

corename_example_design/simulation/corename_example_sim/submodules

corename_example_design/example_project/corename_example/submodules

This issue will be fixed in a future version of the Quartus® II software.

Download the Verilog file from the link below:

alt_mem_ddrx_csr.v (Verilog)

Workaround/Fix

The workaround is to download the attached version of the alt_mem_ddrx_csr.v file and overwrite the four instances in the following directories:

corename/

corename_sim/altera_mem_if_nextgen_ddr3_controller_core/

corename_example_design/simulation/corename_example_sim/submodules

corename_example_design/example_project/corename_example/submodules

This issue will be fixed in a future version of the Quartus® II software.

Download the Verilog file from the link below:

 

alt_mem_ddrx_csr.v (Verilog)