You may see a larger than expected tRCD delay in DDR3 UniPHY quarter-rate memory controllers because the transactions are generated by the controller clock which is running at a quarter of the memory clock rate (1 ctl_clk = 4 mem_ck). The controller has the ability to issue 2 commands per controller clock, one row command like ACTIVATE or PRECHARGE and one column command like WRITE or READ. When tRCD is 11 that refers to 11 mem_ck or 2.75 (11/4) ctl_clk. This value is rounded up to 3 ctl_clk or 12 mem_ck. Additionally, each controller clock can be divided into four phases, a phase for each mem_ck cycle occurring per controller clock. The controller is designed to send row commands during phase one and column comands during phase three of each controller clock cycle. This adds an additional 2 mem_ck of delay to tRCD. For this example, the final delay for tRCD is 12 + 2 or 14 mem_ck.
Device Family: Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Cyclone® V E, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX
Area: EMIF, Intellectual Property