Device Family: Arria® V GT, Arria® V GX, Arria® V ST, Arria® V SX, Cyclone® V E, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX

Type: Answers

Area: EMIF, Intellectual Property

IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Critical warning: _p0_pin_map.tcl: Failed to find PLL clock for pins


For Arria®  V and Cyclone®  V Hard Memory Controller (HMC) designs, you will see the following critical warning if the MPFE clocks (mp_cmd_clk_0_clk, mp_rfifo_clk_0_clk, mp_wfifo_clk_0_clk) are generated by a stand-alone PLL and not the HMC PLL:

Critical warning: <Instance_name>_p0_pin_map.tcl: Failed to find PLL clock for pins 

Warning: <Instance_name>_p0_pin_map.tcl: Could not find all DRIVER CORE CK pins


You need to apply the following workaround:

Step 1)  Open the <Instance_name>_p0_pin_map.tcl file and change 

if {[get_collection_size [get_registers -nowarn (driver_core_ck_pins)]] > 0} {


if {[string compare -nocase (driver_core_ck_pins) ""] != 0 && [get_collection_size [get_registers -nowarn (driver_core_ck_pins)]] > 0} {

Step 2) In the <Instance_name>_p0.sdc file, change the pll_driver_core_clock to the clock that drives the MPFE clock inputs (mp_cmd_clk_0_clk, mp_rfifo_clk_0_clk, mp_wfifo_clk_0_clk).

This issue will be fixed in a future release of the Quartus® II software.