Type: Answers

Type: How-To

Area: EMIF

Area: Intellectual Property


IP Product: Other

Is there any issue when instance the DDR3 hard IP core?

Description

Yes, there is an issue when instance the DDR3 hard IP core with these ports:

mp_cmd_clk_0_clk, mp_rfifo_clk_0_clk, mp_wfifo_clk_0_clk.

Workaround/Fix

Remove these ports from the top level when instance the DDR3 hard IP core if not use, or drive them by a clock buffer .

For example to add clk buffer like this:


wire  clk_source;


altclkctrl #(  .clock_type("GLOBAL CLOCK"), .number_of_clocks(1) )

global_clk_inst1 ( .inclk(clk_source),.outclk(mp_cmd_clk_0_clk));.