Description
You may get this warning in the Quartus® II software when synthesizing an unsigned integer in Verilog HDL as shown in the below example:
reg [8:0] COUNT;
always @ (posedge CLK or posedge RST)
begin
COUNT = COUNT 1;
You get this warning because 1 is an unsized integer literal which defaults to 32 bits.
Resolution
To avoid this warning, use 1'b1 rather than 1.
COUNT = COUNT 1'b1;