Device Family: Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Cyclone® V E, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX

Type: Answers

Area: Component, EMIF

IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Can I swap DQ pins of the HMC to ease routing congestion?


After assigning the dedicated DQ pins of the FPGA according to the index on the mem_dq port, it is OK to swap the data bits on the board. Please make sure to only swap data bits within the same DQS group (byte lane). You can also swap DQS groups by swapping all the signals in a DQS group (DQ/DQS/DM) with the corresponding signals in another DQS group.