Type: Answers

Type: How-To

Area: EMIF

Area: Intellectual Property


IP Product: DDR3 SDRAM Controller supporting ALTMEMPHY

Are there any concern on DDR timing using Altera EMIF (External Memory Interface) IP if my design fails DCD (Duty Cycle Distortion) compliance testing?

Description

If your design fails DCD compliance testing, system functionality still can be guaranteed over PVT (Process, Voltage and Temperature) if the following are true:

All memory timing parameters are set correctly in EMIF IP GUI (Graphical User Interface), according to the memory speed grade and refer to the memory vendor data sheet

All the board-level effects are entered correctly under Board Settings tab. You must use HyperLynx or a similar simulator to obtain these values that are representative of your board.

EMIF timing analysis in your design is of positive margin from TimeQuest Timing Analysis

  • Altera Quartus® II software external memory interface timing analysis is a full system level analysis including PCB effects such as ISI, SSI, FPGA effects such as rise/fall modeling on DQ/DQS/CK as well as DCD, and memory device effects such as tDQSQ, tQH, tDS, tDH, tIS, tIH, tDQSCK, memory calibration.

Workaround/Fix