Device Family: Arria® V GT, Arria® V GX, Cyclone® V E, Cyclone® V GT, Cyclone® V GX, Cyclone® V SX

Type: Answers

Area: EMIF, Intellectual Property

IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Internal Error: Sub-system: FSV, File: /quartus/fitter/fsv/fsv_module_mint.cpp, Line: 1869 driver_atom->is_clkbuf()


You may receive this Internal Error when implementing a DDR2 SDRAM memory interface or DDR3 SDRAM memory interface using the Hard Memory Controller in a Cyclone®  V or Arria®  V device family. Quartus® II software expects the clock inputs (mp_cmd_clk_0_clk, mp_rfifo_clk_0_clk and mp_wfifo_clk_0_clk) of the Hard Memory Controller to be always driven by a clock buffer. It automatically inserts a clock buffer whenever these ports are conencted through a PLL. The internal error may occur if these ports are just connected to external input ports.


There are two workarounds for this issue. The first workaround is to insert clock buffers to drive the clock inputs of the Hard Memory Controller manually. The second workaround is to add the following global signal assignments so that the clock buffers are automatically inserted for the input clock ports:


set_instance_assignment -name GLOBAL_SIGNAL "REGIONAL CLOCK" -to {mp_cmd_clk_0_clk name}

set_instance_assignment -name GLOBAL_SIGNAL "REGIONAL CLOCK" -to {mp_rfifo_clk_0_clk name}

set_instance_assignment -name GLOBAL_SIGNAL "REGIONAL CLOCK" -to {mp_wfifo_clk_0_clk name}


This issue will be addressed in a future version of the Quartus II software.