Device Family: Stratix® IV GX

Type: Answers

Area: Component, HSIO


IP Product: Other

What is the behavior of the byte ordering block when I enable two-symbol byte ordering option in basic double-width mode of the ALTGX Megawizard interface for the Stratix IV GX device?

Description

For Stratix® IV GX devices, the ALTGX MegaWizard® Plug-in Manager provides an option to select two-symbol byte ordering for basic double-width configuration. This option is available in the Rate Matcher/Byte Order screen.

 

When you simulate the Stratix® IV GX transceiver instance in the above configuration, the expected behavior is that the rx_ byteorderalignstatus output port should get asserted if the received data matches both the MSByte and LSByte of programmed byte ordering pattern.

 

Altera has identified that in Quartus® II software version 8.0, for the basic double width mode configuration with two symbol byte ordering option enabled, the  rx_byteorderalignstatus port is asserted if the LSByte of the programmed byte ordering pattern is received irrespective of the value on the MSByte