Device Family: Intel® Arria® 10 GT

Device Family: Intel® Arria® 10 GX

Device Family: Intel® Arria® 10 SX

Device Family: Arria® II GX

Device Family: Arria® II GZ

Device Family: Arria® V GT

Device Family: Arria® V GX

Device Family: Arria® V GZ

Device Family: Arria® V ST

Device Family: Arria® V SX

Device Family: Cyclone® II

Device Family: Cyclone® III

Device Family: Cyclone® III LS

Device Family: Cyclone® IV E

Device Family: Cyclone® IV GX

Device Family: Cyclone® V E

Device Family: Cyclone® V GT

Device Family: Cyclone® V GX

Device Family: Cyclone® V SE

Device Family: Cyclone® V ST

Device Family: Cyclone® V SX

Device Family: Intel® Stratix® 10 GX

Device Family: Intel® Stratix® 10 SX

Device Family: Stratix® II

Device Family: Stratix® II GX

Device Family: Stratix® III

Device Family: Stratix® IV E

Device Family: Stratix® IV GT

Device Family: Stratix® IV GX

Device Family: Stratix® V E

Device Family: Stratix® V GS

Device Family: Stratix® V GT

Device Family: Stratix® V GX

Type: Answers

Area: Intellectual Property


IP Product: Triple Speed Ethernet with 1588 MegaCore

Why is the aFrameCheckSequenceErrors counter of the Triple Speed Ethernet (TSE) IP core incremented when alignment errors occur?

Description

Due to a bug in the Triple Speed Ethernet (TSE) IP core, starting in IP version 13.0, the aFrameCheckSequenceErrors counter may be incremented when alignment errors occur. A frame with alignment errors should be recognized as an invalid frame, hence aFrameCheckSequenceErrors should not be incremented.

Workaround/Fix

This bug is fixed in IP core version 14.1 and later.