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Type: Answers

Area: Intellectual Property


IP Product: Triple Speed Ethernet with 1588 MegaCore

Why does the Triple Speed Ethernet IP core fail to report collisions correctly when operating in half-duplex mode?

Description

The Triple Speed Ethernet (TSE) IP core may fail to correctly assert the EXCESS_COL (Bit 11) and LATE_COL (Bit 12) fields of the Command_Config register and the rx_err[5] collision error signal.

Workaround/Fix

This problem is scheduled to be fixed in a future release of the IP core.