Device Family: Stratix® III, Stratix® IV E, Stratix® IV GT, Stratix® IV GX, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Is there an issue with Error Correcting Code (ECC) feature in DDR3 SDRAM and DDR2 SDRAM UniPHY based controller in version 11.0?

Description

Yes, there an issue with Error Correcting Code (ECC) with auto error correction feature in DDR3 SDRAM and DDR2 SDRAM UniPHY based controller in version 11.0. If you have a single bit error in the data being written to the memory, the memory controller will write the data with the single bit error in to the memory, read it back with the single bit error, correct it at the local side so that the data read by the user logic is correct. Although it corrects the data at the user logic or local side, it does not write the corrected data back to the memory device like it is supposed to.    

The issue is because parameter "CTL_ECC_RMW_ENABLED" is not passed down to the controller instance so the controller does not perform read modified write since auto correction feature does not get enabled.

The workaround is to -

- Open <instance_name>.v

- Add the following line in "alt_mem_if_ddr3_controller_top" instantation:

          - ".CTL_ECC_RMW_ENABLED (1),"

This will cause auto-correction feature to be enabled.

The issue will be fixed in the future version of the Quartus® II software and IP.