Device Family: Stratix® III

Device Family: Stratix® IV E

Device Family: Stratix® IV GT

Device Family: Stratix® IV GX

Type: Answers

Area: EMIF

Area: Intellectual Property


IP Product: RLDRAM II Controller with UniPHY

Why do I get timing violation associated with CK clock domain when implement multiple RLDRAM II interfaces sharing a single PLL and DLL?

Description

When implementing multiple RLDRAM II interfaces sharing a single PLL and DLL on Stratix® III or Stratix IV in Quartus® II software version 11.1SP2, the CK/DK analysis may show false timing violations that should be cut. The false timing violations occur because each interface gives a different SDC clock name to the common clock buffer. Every new clock name results in a set of new timing paths, which are not covered by the existing false-path constraints.

Workaround/Fix