Device Family: Arria® II GZ, Arria® V GX, Cyclone® V GX, Stratix® IV E, Stratix® IV GT, Stratix® IV GX, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property

IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Why the Maximum Avalon-MM burst length options in DDR2/DDR3 SDRAM UniPHY based Controller does not match with the other Qsys component like Maximum burst size (words) in Avalon-MM Pipeline Bridge?

Description

You may see the DDR2/DDR3 SDRAM UniPHY based Controller has Maximum Avalon-MM burst length options {1, 3, 7, 15, 31, 63, 127, 255, 511, 1023, 2047}.

While Avalon-MM Pipeline Bridge has Maximum burst size (words) options {1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024} in Quartus® II software version 11.1SP2.

The Maximum Avalon-MM burst length value choices in DDR2/DDR3 SDRAM UniPHY based Controller is incorrect and we will revert it back to {1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024} in the future version of Quartus II software.

Workaround/Fix

The actual maximum burst length implied by the “Maximum Avalon-MM burst length” options in DDR2/DDR3 SDRAM UniPHY based Controller is shown below:

1 -> 1

3 -> 2

7 -> 4

15 -> 8

31 -> 16

63 -> 32

127 -> 64

255 -> 128

511 -> 256

1023 -> 512

2047 -> 1024

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