Type: Answers

Area: Component, EMIF


IP Product: DDR3 SDRAM Controller supporting ALTMEMPHY

Does DDR3 SDRAM and DDR2 SDRAM Altmemphy and UniPHY based controller with Error Correction Coding (ECC) enabled support partial write for DIMMs without DM pins?

Description

avl_be port is not exported if DM pin generation option is disabled. If you want to implement partial write functionality, you will have to export "local_be" port from <instance_name>_controller_phy.v/vhd module to <instance_name>.v/vhd module.

For example, if you want to issue write request local_size of 1 to address 0, you should issue write request local_size of 2 to address 0 but the byte enable for the second burst is set to 0.