Device Family: Arria® V

Device Family: Arria® V GX

Type: Answers

Area: Intellectual Property


IP Product: Triple Speed Ethernet MAC

Warning: OUTCLK port on the PLL is not properly connected on &lt;instance&gt;. The output clock port on the PLL must be connected. <br>Info: Must be connected

Description

When you compile the Triple Speed Ethernet (TSE) IP in LVDS mode for Arria® V devices, you will get the following warning messages during Analysis & Synthesis: 

 

Warning: OUTCLK port on the PLL is not properly connected on <instance>. The output clock port on the PLL must be connected.

    Info: Must be connected

Workaround/Fix

The reason for this warning is due to ALTLVDS_RX generating a slow PLL clock even though it is in soft-CDR mode and only the DPA clock is being used.

The warning simply indicates that the slow clock PLL has no fanouts.

 

Hence, this warning message can be safely ignored.