Device Family: Arria® V GT

Device Family: Arria® V GX

Device Family: Arria® V GZ

Device Family: Arria® V ST

Device Family: Arria® V SX

Device Family: Cyclone® V E

Device Family: Cyclone® V GT

Device Family: Cyclone® V GX

Device Family: Cyclone® V SE

Device Family: Cyclone® V ST

Device Family: Cyclone® V SX

Type: Answers

Area: EMIF

Area: Intellectual Property


IP Product: Cyclone V GX FPGA Development Kit

How do I connect the signals of the ALTDQ_DQS2 Hard Read FIFO?

Description

The ALTDQ_DQS2 Hard Read FIFO has the following ports as described below:

lfifo_rden: Data input to the Read FIFO Read Enable. This signal is the full read enable token generated by user logic and is asserted for the length of the desired read burst.

rfifo_reset_n: Active low reset to the Read FIFO.

vfifo_qvld: This signal is used as the write enable on the Read FIFO in all cases where the capture strobe is not bidirectional.