Device Family: Stratix® III, Stratix® IV E, Stratix® IV GT, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

How do I connect csr_debugaccess and csr_burst_count ports generated by DDR3 SDRAM Controller with UniPHY?

Description

You will see the ports csr_debugaccess and csr_burst_count ports being generated by the DDR3 SDRAM Controller IP with UniPHY in Quartus® II software version 11.0 when you have enabled Configuration and Status Register (CSR) option. These ports are being exported even though the they are not being enabled by the CSR port.

You can tie csr_debugaccess to 0 and csr_burst_count to 1.

The definitions of these two signals are in the Avalon Interface Specification (PDF) document.

The ports will be removed in the future version of the IP.