Device Family: Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property

IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Why do I get minimum period timing violation in UniPHY based DDR3 SDRAM Controller on Stratix V device?


You may see minimum period violations on address or command data-path in Quartus® II software version 11.1SP2 and earlier if the UniPHY based DDR3 SDRAM memory interface design in Stratix® V device is combined with user logic that has packed registers in the periphery.


This issue will be fixed in the future version of Quartus II software