When you implement a design including DDIO block in Quartus® II software version 13.0, an internal error may be seen when the design is not properly implemented.
Area: Intellectual Property
The clock of the ddio block should be connected to clock source but not GND or VCC. If you use Altera® DDR IP, you should check the port connection to make sure all signals are carefully wired.
We will fix this internal error into a more readiness error in further release.