Type: Answers

Area: EMIF

Area: Intellectual Property

Last Modified: June 30, 2013
Version Found: v13.0
IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY
Bug ID: n/a

Internal Error: Sub-system: ASMIO, File: /quartus/comp/asmio/asmio_dqs_s5.cpp, Line: 2330 found_oct_hr_clk ^ found_hr_clk_in


When you implement a design including DDIO block in Quartus® II software version 13.0, an internal error may be seen when the design is not properly implemented.


The clock of the ddio block should be connected to clock source but not GND or VCC. If you use Altera® DDR IP, you should check the port connection to make sure all signals are carefully wired.

We will fix this internal error into a more readiness error in further release.