Device Family: Arria® II GX, Arria® V GX, Arria® V GZ, Cyclone® V GX, Stratix® IV GX, Stratix® V GX

Type: Answers

Area: Component, EMIF

Why assertion of reset may cause low probablity lock up of UniPHY NIOS sequencer resulting in incomplete calibration


UniPHY IP does not complete calibration after asserting and deasserting global_reset_n or soft_reset_n signal low for UniPHY IP. EMIF debug toolkit cannot be connected to that interface (link project to device). This condition does not change even if multiple resets are issued later.   This condition can be recovered only by reconfiguring the device.

These symptoms can be caused by the internal reset structure of the EMIF UniPHY IP.  An asynchronous reset assertion to the logic driving the address bus of an M20K RAM can cause asynchronous logic propagation.  This can impact functionality of M20K address row/column decoders, opening more than one word line which can result in charge sharing between bit cells, corrupting the contents of the M20K.  Note that the probability of M20K corruption due to asynchronous reset assertion is very low.

PLL reset during M20k read or write operation can also contribute to embedded RAM/ROM corruption because PLL lock loss may result in a clock glitch during reset and this may impact functionality of M20K address row/column decoders.

This corruption affects the UniPHY IP because it contains a Nios (R) II processor that is used for calibration, and the processor's program code is stored in M20K RAM.  If the corruption occurs within the Nios (R) II program memory, this can cause the Nios (R) II sequencer to lock up, resulting in incomplete calibration.  Recovery from this situation is only possible by reprogramming the device, as M20K contents are only loaded during device programming.

It is important to note that common EMIF failures listed below does not necessarily mean the M20K RAM is corrupted or Nios (R) II sequencer is locked up

-        If calibration never passes (i.e. calibration always fails).

-        If calibration margins are very slim, and occasionally fail calibration.

-        If design passed calibration, and occasional data errors are observed while running the design.

-        If design says it passed calibration, but design is not working as expected.



UniPHY IP core has two reset inputs

Global_reset_n: is connected to everything in UniPHY IP including PLL.

Soft_reset_n: is connected to everything in UniPHY IP except PLL.

1.     Altera strongly recommends using only soft_reset_n at all times.  Use global_reset_n only for Power on reset.

To reset PLL during Power on, Use the following sequence

a.      Assert Global_reset_n (PLL reset )

b.     Power up and reconfigure the chip

c.      De-assert Global_reset_n

2.   The fix changes the internal reset controller and reset structure of the UNIPHY IP core to use synchronous resets, as well as pre-emptively deasserting the M20K clock_enable port during a reset condition.  This prevents any metastable transitions from propagating into the M20K address decoder.

This fix will be provided as part of 13.0dp1, 13.0sp1, and all subsequent versions of Quartus.  Users will need to regenerate the UnipHY IP and recompile the design.  Altera recommends moving to one of these versions of Quartus.

If a fix is required more urgently, or a fix is required for Quartus version 12.1sp1, the UniPHY IP core can be manually updated.  The following procedure must be followed:

Locate the source files for the Altera UniPHY IP within your design.
There are 5 files that need to be modified.






1.     Download altera_reset_synchronizer.v  from the following link and place in the same directory as the  UniPHY IP source files:


2.     Download altera_reset_controller.v from the following link and place in the same directory as the UniPHY IP source files:

3.     In’ – Ensure that the input ‘s1_clken’ connects to the ‘clocken0’ input of the ‘the_altsyncram’

4.     In instance<interface_name>_if0_p0_reset.v – modify the defparam statements for the “dut_if0_p0_reset_sync” instances so that the parameters “RESET_SYNC_STAGES” and “NUM_RESET_OUTPUT” are set according to the attached sample file (dut_if0_p0_reset.v). (Do not download the sample file in the UniPHY IP source file directory) (sample file  for <interface_name_if0_p0_reset.v)


5.     In <interface_name>_if0_s0.v

(Do not download the sample file dut_if0_s0.v  in the UniPHY IP source file directory) (sample file for <interface_name>_if0_s0.v )

Add the following port to the top level:

              wire early_rst_controller_reset_out_reset; 

- Wire the output port “m20k_gate” on the “rst_controller”  module to the ‘s1_clken’ input of ‘sequencer_mem’ module.  Since the M20k_gate output is active-low, you need to invert the output as follows:

    .s1_clken      (~early_rst_controller_reset_out_reset), // on sequencer_mem,  line 785 of the attached sample file (dut_if0_s0.v)

               .m20k_gate  (early_rst_controller_reset_out_reset), // on rst_controller,  line 2572 of the attached sample file

6.     Once these changes have been made, your design will need to be recompiled.