Device Family: Stratix® III

Device Family: Stratix® IV GX

Device Family: Stratix® V GX

Type: Answers

Area: EMIF

Area: Intellectual Property


IP Product: DDR3 SDRAM Controller supporting ALTMEMPHY

Why do I get two chip selects when I generate a UniPHY DDR3 registered DIMM single rank configuration?

Description

Registered DIMMs contain a register for the memory address, command, and clock signals. This register has to be programmed with control words during initialization and this occurs when both chip select 0 and 1 are active low. Typically, there are sixteen control word accesses.

After the register has been initialized, the RDIMM memory is then accessed using chip select 0. Chip select 1 is only used during register initialization.

To observe this, it is recommended to run the simulation of the example design of a single rank DDR3 registered DIMM configuration and look at the signal waveforms.

Workaround/Fix