This error will only occur if you have modified the VHDL Output File (.vho) or Verilog Output File (.vo) by removing the reference to the Standard Delay Format Output File (.sdo).
ModelSim will flag this error when the SDO is applied to the wrong instance. By default, the SDO file is referenced in the QuartusTM- or MAX+PLUS® II-generated VO or VHO files.
When you use a test bench to simulate a VHO or VO file generated by the Quartus or MAX+PLUS II software, the SDO file must be applied to the entity in the VHO or the VO file and not the top-level test bench entity.
To apply the SDO file to the correct instance, follow the steps below:
- Open the Load Design dialog box in ModelSim.
- Click on the SDF tab and then click on the Add button.
- Browse and choose the SDO file.
- In the Apply to Region box, type the path of the instance to which the SDO file should be applied.
- Click OK.